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19-3861; Rev 0; 10/05
22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipsets MAX9223/MAX9224
General Description
The MAX9223/MAX9224 serializer/deserializer chipsets reduce wiring by serializing 22 bits onto a single differential pair. 22 bits are serialized in each cycle of the parallel input clock resulting in a 110Mbps to 220Mbps net serial-data rate ideal for cell phone QVGA and QCIF displays. The MAX9223 serializes the 18-bit RGB, VSYNC, HSYNC, and two control signals from the baseband processor to reduce wiring through the hinge to the LCD controller. The 2-wire serial interface uses low-current differential signaling (LCDS) for low EMI, high commonmode noise immunity, and ground-shift tolerance. The MAX9223/MAX9224 automatically identify the word boundary in serial data in case of signal interruption. The MAX9224 power-down is controlled by the MAX9223. The MAX9223 and MAX9224 consume 3.5A or less in power-down mode. The MAX9223 serializer operates from a single +2.375V to +3.465V supply and accepts +1.71V to +3.465V inputs. The MAX9224 deserializer operates from a +2.375V to +3.465V core supply and has a separate output buffer supply (V DDO ), allowing +1.71V to +3.465V output high levels. The MAX9223/MAX9224 are specified over the -40C to +85C extended temperature range and are available in 28-pin TQFN (4mm x 4mm x 0.8mm) packages with an exposed paddle.
Features
o Ideal for Serializing Cell Phone LCD or Imager Parallel Interface o MAX9223 Serializes 18-Bit RGB, VSYNC, HSYNC, and Two Control Signals o LCDS Rejects Common-Mode Noise o Automatic Location of Word Boundary After Signal Interruption o Power-Down Control Through the Serial Link o Power-Down Supply Current 0.5A (max)--MAX9223 3.0A (max)--MAX9224 o +2.375V to +3.465V Core Supply Voltage o Parallel I/O Interfaces Directly to 1.8V to 3.3V Logic o 15kV Human Body Model ESD Protection o -40C to +85C Operating Temperature Range
Ordering Information
PART MAX9223ETI MAX9223ETI+ MAX9224ETI MAX9224ETI+ TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PINPACKAGE 28 TQFN-EP* 28 TQFN-EP* 28 TQFN-EP* 28 TQFN-EP* PKG CODE T2844-1 T2844-1 T2844-1 T2844-1
Applications
Cell Phones LCDs Digital Cameras
+Denotes lead-free package. *EP = Exposed paddle. Pin Configurations appear at end of data sheet.
Typical Application Circuit
LCDS PARALLEL DATA IN LATCH INPUT
PARALLEL TO SERIAL
SERIAL TO PARALLEL
OUTPUT LATCH
PARALLEL DATA OUT
PIXEL CLOCK IN
TIMING AND CONTROL
POWER-DOWN CONTROL TIMING AND CONTROL
DLL
PIXEL CLOCK OUT
MAX9223
MAX9224
________________________________________________________________ Maxim Integrated Products
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
ABSOLUTE MAXIMUM RATINGS
VDD to GND ...........................................................-0.5V to +4.0V VDDO to GND.........................................................-0.5V to +4.0V Serial Interface (SDO+, SDO-, SDI+, SDI-) to GND .....................................................-0.5V to +4.0V Single-Ended Inputs (DIN_, PCLKIN, PWRDN) to GND ....................................-0.5V to (VDD + 0.5V) Single-Ended Outputs (DOUT_, PCLKOUT) to GND ..............................-0.5V to (VDDO + 0.5V) Continuous Power Dissipation (TA = +70C) 28-Pin TQFN (4mm x 4mm x 0.8mm) Multilayer PC Board (derate 28.6mW/C above +70C).............................................................2286mW Single-Layer PC Board (derate 20.8mW/C above +70C).............................................................1667mW Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C ESD Protection (Human Body Model) SDO+, SDO-, SDI+, SDI- to GND ...............................> 15kV All Other Pins ................................................................> 2kV
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS--MAX9223
(VDD = +2.375V to +3.465V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +2.5V, TA = +25C.) (Notes 1, 2)
PARAMETER High-Level Input Voltage Low-Level Input Voltage Input Current LCDS OUTPUT (SDO+, SDO-) Differential Output Current (Note 3) Output Short-Circuit Current POWER SUPPLY VDD = 2.5V, DIN_ = all low or all high PCLKIN = 5MHz (110Mbps) PCLKIN = 10MHz (220Mbps) PCLKIN = 5MHz (110Mbps) PCLKIN = 10MHz (220Mbps) 4.4 5.6 4.1 5.4 8.2 mA 8.2 10.6 mA 10.6 0.5 A IODH IODL IOS High level Low level Shorted to 0V or VDD 600 200 643 229 880 300 880 A A SYMBOL VIH VIL VIN = 0V to VDD IIN -0.3V VIN < 0V VDD < VIN (VDD + 0.3V) CONDITIONS MIN 1.19 -0.3 -20 -100 TYP MAX VDD + 0.3 +0.3 +20 +100 A UNITS V V SINGLE-ENDED INPUTS (PCLKIN, DIN_, PWRDN)
Supply Current
IDD
Worst-Case Pattern Supply Current
IDDW
VDD = 2.5V, Figure 1 All inputs = low
Power-Down Supply Current
IDDZ
2
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset
DC ELECTRICAL CHARACTERISTICS--MAX9224
(VDD = +2.375V to +3.465V, VDDO = +1.71V to +3.465V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = VDDO = +2.5V, TA = +25C.) (Notes 1, 2)
PARAMETER High-Level Output Voltage Low-Level Output Voltage Output Short-Circuit Current LCDS INPUT (SDI+, SDI-) Differential Input-Current Threshold Common-Mode Input Current IID IIC IIC = 0A at VDD = 3.3V 5% IIC = 0A at VDD = 2.8V 5% Differential Input Impedance ZID IIC = 0A at VDD = 2.5V 5% IIC = 300A at VDD = 3.3V 5% IIC = 300A at VDD = 2.8V 5% Common-Mode Input Impedance Input Capacitance POWER SUPPLY VDD = VDDO = 2.5V DOUT_ = all high or all low PCLKOUT = 5MHz (110Mbps) PCLKOUT = 10MHz (220Mbps) PCLKOUT = 5MHz (110Mbps) PCLKOUT = 10MHz (220Mbps) 9 9 10 10 0.08 MAX9223 VDD to MAX9224 VDD MAX9223 to MAX9224 ground difference -5 -0.2 12 mA 12 12 mA 12 3 +5 +0.2 A % V ZIC CIN IIC = 300A SDI+ or SDI- to ground -300 69 82 95 67 86 90 400 500 90 108 125 91 108 167 2 +300 109 132 153 112 136 375 pF A A SYMBOL VOH VOL IOS CONDITIONS VDDO = +2.375V to +3.465V, IOH = -1mA VDDO = +2.375V to +3.465V, IOL = 1mA Output shorted to ground VDDO = 2.375V VDDO = 3.135V VDDO = 3.465V -2 -9 -20 mA MIN 0.8 x VDDO 0.2 TYP MAX UNITS V V SINGLE-ENDED OUTPUTS (PCLKOUT, DOUT_)
MAX9223/MAX9224
Supply Current (Note 4)
ITOT
Worst-Case Pattern Supply Current (Note 4) Power-Down Supply Current (Note 4) Supply Difference GROUND POTENTIAL Ground Difference
ITOTW
CL = 5pF, VDD = VDDO = 2.5V, Figure 2
ITOTZ VSD VGD
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
AC ELECTRICAL CHARACTERISTICS--MAX9223
(VDD = +2.375V to +3.465V, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = +2.5V, TA = +25C.) (Note 3)
PARAMETER Input Rise Time Input Fall Time PCLKIN Period High-Level Pulse Width Low-Level Pulse Width Setup Time Hold Time SYMBOL tR tF tP tPWH tPWL tS tH 100 0.3 x tP 0.3 x tP 3 1 CONDITIONS MIN TYP MAX 2 2 200 0.7 x tP 0.7 x tP UNITS ns ns ns ns ns ns ns PCLKIN INPUT REQUIREMENTS (Figure 3)
AC ELECTRICAL CHARACTERISTICS--MAX9224
(VDD = VDDO = +2.375V to +3.465V, CL = 5pF, TA = -40C to +85C, unless otherwise noted. Typical values are at VDD = VDDO = +2.5V, TA = +25C.) (Notes 3, 5)
PARAMETER PCLKOUT Period High-Level Pulse Width Low-Level Pulse Width Data Valid Before PCLKOUT Data Valid After PCLKOUT SERIALIZER AND DESERIALIZER LINK tPU1 Power-Up Time tPU2 Power-Down Time tPWRDN From VDD = VDDO = 2.375V when supplies are ramping up From PWRDN low to high From PWRDN high to low 2.8 6144 x tP 4096 x tP 10 SYMBOL tP tPWH tPWL tVB tVA Figure 4 Figure 4 Figure 4 Figure 4 Figure 4 CONDITIONS MIN 100 0.4 x tP 0.4 x tP 5 5 TYP MAX 200 0.6 x tP 0.6 x tP UNITS ns ns ns ns ns
ns
s
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +85C. Note 3: Parameters are guaranteed by design and characterization, and are not production tested. Limits are set at 6 sigma. Note 4: ITOT = IDD + IDDO. Note 5: CL includes probe and test jig capacitance.
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
Test Circuits/Timing Diagrams
ODD DIN_ EVEN DIN_ PCLKIN
ODD DOUT_ EVEN DOUT_ PCLKOUT
Figure 1. Serializer Worst-Case Switching Pattern
Figure 2. Deserializer Worst-Case Switching Pattern
tP tPWL VIH PCLKIN
tF
tPWH VIH VIH
VIL
VIL tR tS tH VIH VIL
DIN_ PWRDN
VIH VIL
VIH IS THE MINIMUM HIGH-LEVEL INPUT AND VIL IS THE MAXIMUM LOW-LEVEL INPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE)
Figure 3. Serializer Input Timing
tP tPWL VOH PCLKOUT VOL VOL VOH tPWH VOH
tVB DOUT_ VOH VOL
tVA VOH VOL
VOH IS THE MINIMUM HIGH-LEVEL OUTPUT AND VOL IS THE MAXIMUM LOW-LEVEL OUTPUT (SEE THE DC ELECTRICAL CHARACTERISTICS TABLE)
Figure 4. Deserializer Output Timing
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
Typical Operating Characteristics
(VDD = VDDO = +2.8V, logic input levels = 0 to +2.8V, logic output load CL = 5pF, TA = +25C, unless otherwise noted.)
MAX9223 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9233/4 toc01
MAX9223 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9233/4 toc02
MAX9223 SUPPLY CURRENT vs. SUPPLY VOLTAGE
DIN[21:0] = WORST-CASE SWITCHING PATTERN
MAX9233/4 toc03 MAX9233/4 toc09 MAX9233/4 toc06
10
DIN[21:0] = ALL LOW PCLKIN = 10MHz
10
DIN[21:0] = ALL HIGH
10
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
8
8 PCLKIN = 10MHz 6
8
PCLKIN = 10MHz
6
6
4
PCLKIN = 5MHz
4 PCLKIN = 5MHz
4 PCLKIN = 5MHz 2
2 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
2 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
2.3
2.5
2.7
2.9
3.1
3.3
3.5
SUPPLY VOLTAGE (V)
MAX9223 SUPPLY CURRENT vs. FREQUENCY
MAX9233/4 toc04
MAX9223 SUPPLY CURRENT vs. FREQUENCY
DIN[21:0] = ALL HIGH VDD = 3.3V SUPPLY CURRENT (mA) VDD = 2.8V 6
MAX9233/4 toc05
MAX9223 SUPPLY CURRENT vs. FREQUENCY
8 DIN[21:0] = WORST-CASE SWITCHING PATTERN VDD = 3.3V VDD = 2.8V SUPPLY CURRENT (mA) 6
10
DIN[21:0] = ALL LOW VDD = 3.3V
8
SUPPLY CURRENT (mA)
8
VDD = 2.8V
6
4
4
VDD = 2.5V
VDD = 2.5V
4
VDD = 2.5V
2 5 6 7 8 9 10 FREQUENCY (MHz)
2 5 6 7 8 9 10 FREQUENCY (MHz)
2 5 6 7 8 9 10 FREQUENCY (MHz)
MAX9223 POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9233/4 toc07
MAX9224 SUPPLY CURRENT vs. SUPPLY VOLTAGE
DOUT[21:0] = ALL LOW PCLKOUT = 10MHz
MAX9233/4 toc08
MAX9224 SUPPLY CURRENT vs. SUPPLY VOLTAGE
12 DOUT[21:0] = ALL HIGH PCLKOUT = 10MHz
0.20
0.16 SUPPLY CURRENT (A)
PCLKIN = LOW PWRDN = LOW DIN[21:0] = ALL LOW
12
11 SUPPLY CURRENT (mA)
11 SUPPLY CURRENT (mA)
0.12
10
10
0.08
9 PCLKOUT = 5MHz 8
9 PCLKOUT = 5MHz
0.04
8
0 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
7 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
7 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
6
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
Typical Operating Characteristics (continued)
(VDD = VDDO = +2.8V, logic input levels = 0 to +2.8V, logic output load CL = 5pF, TA = +25C, unless otherwise noted.)
MAX9224 SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9233/4 toc10
MAX9224 SUPPLY CURRENT vs. FREQUENCY
MAX9233/4 toc11
MAX9224 SUPPLY CURRENT vs. FREQUENCY
DOUT[21:0] = ALL HIGH VDD = 3.3V VDD = 2.8V 10
MAX9233/4 toc12
12
11 SUPPLY CURRENT (mA)
DOUT[21:0] = WORST-CASE SWITCHING PATTERN PCLKOUT = 10MHz
12
DOUT[21:0] = ALL LOW VDD = 3.3V VDD = 2.8V
12
11 SUPPLY CURRENT (mA)
11 SUPPLY CURRENT (mA)
10
10
9 PCLKOUT = 5MHz 8
9 VDD = 2.5V 8
9 VDD = 2.5V 8
7 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
7 5 6 7 8 9 10 FREQUENCY (MHz)
7 5 6 7 8 9 10 FREQUENCY (MHz)
MAX9224 SUPPLY CURRENT vs. FREQUENCY
MAX9233/4 toc13
MAX9224 POWER-DOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
MAX9233/4 toc14
MAX9224 DOUT OUTPUT-HIGH VOLTAGE vs. SOURCE CURRENT
MAX9233/4 toc15
12
11 SUPPLY CURRENT (mA)
DOUT[21:0] = WORST-CASE SWITCHING PATTERN VDD = 3.3V VDD = 2.8V
0.6
SDI+/SDI- PULLED UP TO VDD DOUT[21:0] = ALL LOW
2.75 2.50 2.25 DOUT (V) VDDO = 2V VDDO = 2.375V
10
SUPPLY CURRENT (A)
0.5
0.4
2.00 1.75
9 VDD = 2.5V 8
0.3 1.50 VDDO = 1.71V 0.2 1.25 2.3 2.5 2.7 2.9 3.1 3.3 3.5 0 0.2 0.4 0.6 0.8 1.0 SUPPLY VOLTAGE (V) SOURCE CURRENT (mA)
7 5 6 7 8 9 10 FREQUENCY (MHz)
MAX9224 DOUT OUTPUT-LOW VOLTAGE vs. SINK CURRENT
MAX9233/4 toc16
MAX9224 DIFFERENTIAL INPUT IMPEDANCE vs. SUPPLY VOLTAGE
MAX9233/4 toc17
150
VDDO = +1.71V TO +2.375V
160
120
DOUT (mV)
90
INPUT IMPEDANCE () 0 0.2 0.4 0.6 0.8 1.0
140
120
60
30
100
0 SINK CURRENT (mA)
80 2.3 2.5 2.7 2.9 3.1 3.3 3.5 SUPPLY VOLTAGE (V)
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
Pin Description (MAX9223)
PIN 1-12, 14, 15, 21-28 13 16 17 18 19 20 -- NAME DIN13-DIN2, DIN1, DIN0, DIN21-DIN14 PCLKIN PWRDN SDOSDO+ GND VDD EP FUNCTION Single-Ended Parallel Data Inputs. The 22 data bits are loaded into the input latch on the rising edge of PCLKIN. DIN[9:0] are 1.71V to 3.465V tolerant. Internally pulled down to GND. Parallel Clock Input. The rising edge of PCLKIN (typically the pixel clock) latches the parallel data input. Internally pulled down to GND. Power-Down Input. Pull PWRDN low to place the MAX9223 and MAX9224 in power-down mode. Drive PWRDN high for normal operation. Internally pulled down to GND. Inverting LCDS Serial-Data Output Noninverting LCDS Serial-Data Output Ground Core Supply Voltage. Bypass to GND with 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. Exposed Paddle. Connect EP to ground.
Pin Description (MAX9224)
PIN 1, 7, 8, 10-28 NAME DOUT21, DOUT0, DOUT1, DOUT2-DOUT20 VDDO GND SDI+ SDIVDD PCLKOUT EP FUNCTION Single-Ended Parallel Data Outputs. DOUT[21:0] are valid on the rising edge of PCLKOUT. Output Supply Voltage. Bypass to GND with 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. Ground Noninverting LCDS Serial-Data Input Inverting LCDS Serial-Data Input Core Supply Voltage. Bypass to GND with 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin. Parallel Clock Output. Parallel output data are valid on the rising edge of PCLKOUT (typically the pixel clock). Exposed Paddle. Connect EP to ground.
2 3 4 5 6 9 --
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
MAX9223 Functional Diagram MAX9224 Functional Diagram
SDO+ LATCH INPUT
SDI+ SDI-
DIN[21:0]
PARALLEL TO SERIAL
SDO-
SERIAL TO PARALLEL
OUTPUT LATCH
DOUT[21:0]
PCLKIN
TIMING AND CONTROL PWRDN DLL TIMING AND CONTROL PCLKOUT
MAX9223
MAX9224
Detailed Description
The MAX9223 serializer operates at a 5MHz to 10MHz parallel clock frequency, serializing 22 bits of parallel input data DIN[21:0] in each cycle of the parallel clock. DIN[21:0] are latched on the rising edge of PCLKIN. The data and internally generated serial clock are combined and transmitted through SDO+/SDO- using multilevel LCDS. The MAX9224 deserializer receives the LCDS signal on SDI+/SDI-. The deserialized data and recovered parallel clock are available at DOUT[21:0] Serial word format:
G 0 1 2 3 4 5 6 7 8 9 10 11
and PCLKOUT. Output data is valid on the rising edge of PCLKOUT. The first bit (G) is internally grounded and transmitted first. Bit 0 (DIN[0]) is the first valid data bit. Boundary bits OH are used by the MAX9224 deserializer to identify the word boundary and are the inverse polarity of data bit 21 (DIN[21]). Therefore, at least one level transition is guaranteed in one word. The clock is recovered from the serial input.
12
13
14
15
16
17
18
19
20
21
OH OH
LCDS
The MAX9223/MAX9224 use a proprietary multilevel LCDS interface. Figure 5 provides a representation of the data and clock in the multilevel LCDS interface. This interface offers advantages over other chipsets, such as requiring only one differential pair as the transmission medium, the inherently aligned data and clock, and much smaller current levels than the 4mA typically found in traditional LVDS interfaces.
MAX9223/MAX9224 Handshaking
The handshaking function of the MAX9223/MAX9224 provides bidirectional communication between the two devices in case a word boundary error is detected. Prior
to data transmission, the MAX9223 serializer adds boundary bits (OH) to the end of the latched word. These boundary bits are the inverse of the last bit of the latched word. During data transmission, the MAX9224 deserializer continuously monitors the state of the boundary bits of each word. If a word boundary error is detected, the serial link is pulled up to VCC and the MAX9224 powers down. The MAX9223 detects the pullup of the serial link and powers down for 1.0s. After 1.0s, the MAX9223 powers up, causing the power-up of the MAX9224. Then the word boundary is reestablished, and data transfer resumes. The handshaking function is disabled when PWRDN is pulled low.
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
PARALLEL DATA INPUT
PCLK IN
DIN[21:0]
DIN EXAMPLE INPUT
0 1
1 1
2 0
3 1
9 1
10 0
11 0
12 1
13 0
14 1
20 1
21 1
LCDS SERIAL DATA OUTPUT FOR EXAMPLE INPUT (SD0)
G*
1
1
0
1
1
0
0
1
0
1
1
1
OH
OH
*INTERNALLY PREPENDED BIT--ALWAYS 0. NOTE: THERE IS NO TRANSITION BETWEEN OH BITS.
Figure 5. Multilevel LCDS Output Representation
Applications Information
PCLKIN Latch Edge
The parallel data input of the MAX9223 serializer is latched on the rising edge of PCLKIN. Figure 3 shows the serializer input timing.
LCDS output is not driven until the DLL locks. 4096 clock cycles are required for the power-up and link synchronization, before valid DIN can be latched. See Figure 6 for an overall power-up and power-down timing diagram. For normal operation, PCLKIN must be running and settled before driving PWRDN high. If VDD = 0, the LCDS outputs are high impedance to ground and differential.
PCLKOUT Strobe
The serial-data output of the MAX9224 deserializer is valid on the rising edge of PCLKOUT. Figure 4 shows the deserializer output timing.
Ground-Shift Tolerance
The MAX9223/MAX9224 are designed to function normally in the event of a slight shift in ground potential. However, the MAX9224 deserializer ground must be within 0.2V relative to the MAX9223 serializer ground to maintain proper operation.
Power-Down and Power-Off
Driving PWRDN low puts the MAX9223 in power-down mode and sends a pulse to power down the MAX9224. In power-down mode, the DLL is stopped, SDO+/SDO- are high impedance to ground and differential, and the LCDS link is weakly biased around VDD - 0.8V. With PWRDN and all inputs low, the combined MAX9223/MAX9224 supply current is reduced to 3.5A or less. Driving PWRDN high starts DLL lock to PCLKIN and initiates a MAX9224 power-up sequence. The MAX9223
MAX9224 Output Buffer Supply (VDDO)
The MAX9224 parallel outputs are powered from VDDO, which accepts a +1.71V to +3.465V supply, allowing direct interface to inputs with 1.8V to 3.3V logic levels.
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
IN POWERDOWN POWER-UP AND LINK SYNCHRONIZATION DATA TRANSFER POWERDOWN tPWRDN PWRDN IN POWERDOWN
1 PCLKIN
2
4096
DIN_
DON'T CARE
1
N
DON'T CARE
LOW DOUT_
1
N
LOW
PCLKOUT
HIGH
HIGH
Figure 6. MAX9223/MAX9224 Power-Up/Power-Down Sequence
Flex Cable, PC Board Interconnect, and Connectors
Interconnect for LCDS typically has a differential impedance of 110. Use interconnect and connectors that have matched differential impedance to minimize impedance discontinuities.
1M CHARGE-CURRENTLIMIT RESISTOR HIGHVOLTAGE DC SOURCE CS 100pF
RD 1.5k DISCHARGE RESISTANCE STORAGE CAPACITOR DEVICE UNDER TEST
Board Layout and Supply Bypassing
Separate the logic and LCDS signals to prevent crosstalk. A PC board or flex with separate layers for power, ground, and signals is recommended. Bypass each VDD and VDDO pin with high-frequency, surface-mount ceramic 0.1F and 0.01F capacitors in parallel as close to the device as possible, with the smallest value capacitor closest to the supply pin.
Figure 7. Human Body Model ESD Test Circuit
Chip Information
PROCESS: CMOS
ESD Protection
The MAX9223/MAX9224 LCDS inputs and outputs (SDO+/SDO-, SDI+/SDI-) are rated for 15kV ESD protection using the Human Body Model. The Human Body Model discharge components are CS = 100pF and RD = 1.5k (Figure 7).
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset MAX9223/MAX9224
Pin Configurations
DOUT13 DOUT12 DOUT11 PWRDN DOUT10 DOUT9 DOUT8 16 DIN21 SDO+ DOUT7 15 14 13 12 DOUT6 DOUT5 DOUT4 DOUT3 DOUT2 PCLKOUT DOUT1 11 10 9 8 1 DOUT21 2 VDDO 3 GND 4 SDI+ 5 SDI6 VDD 7 DOUT0
TOP VIEW
SDOGND VDD
DIN0
21 DIN20 22 DIN19 23 DIN18 24 DIN17 25 DIN16 26 DIN15 27 DIN14 28 1 DIN13
20
19
18
17
16
15 14 13 12 DIN1 PCLKIN DIN2 DIN3 DIN4 DIN5 DIN6 DOUT14 22 DOUT15 23 DOUT16 24 DOUT17 25 DOUT18 26 DOUT19 27 DOUT20 28
21
20
19
18
17
MAX9223
11 10 9 8
MAX9224
2 DIN12
3 DIN11
4 DIN10
5 DIN9
6 DIN8
7 DIN7
TQFN-EP
TQFN-EP
12
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22-Bit, Low-Power, 5MHz to 10MHz Serializer and Deserializer Chipset
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX9223/MAX9224
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
1 2
PACKAGE OUTLINE, 12, 16, 20, 24, 28L THIN QFN, 4x4x0.8mm
21-0139
E
2 2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2005 Maxim Integrated Products
Springer
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
24L QFN THIN.EPS

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